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| 128Mb DDR SDRAM DDR SDRAM Specification Version 1.0 -1- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Revision History Version 0 (May, 1998) - First version for internal review Version 0.1(June, 1998) - Added x4 organization Version 0.2(Sep,1998) 1. Added "Issue prcharge command for all banks of the device" as the fourth step of power-up squence. 2. In power down mode timing diagram, NOP condition is added to precharge power down exit. Version 0.3(Dec,1998) - Added QFC Function. - Added DC current value - Reduce I/O capacitance values Version 0.4(Feb,1999) -Added DDR SDRAM history for reference(refer to the following page) -Added low power version DC spec Version 0.5(Apr,1999) -Revised following first showing for JEDEC standard -Added DC target current based on new DC test condition Version 0.6(July 1,1999) 1.Modified binning policy From To -Z (133Mhz) -Z (133Mhz/266Mbps@CL=2) -8 (125Mhz) -Y (133Mhz/266Mbps@CL=2.5) -0 (100Mhz) -0 (100Mhz/200Mbps@CL=2) 2.Modified the following AC spec values From. -Z tAC tDQSCK tDQSQ tDS/tDH tCDLR*1 tPRE *1 To. -0 +/- 1ns +/- 1ns +/- 0.75ns 0.75 ns 2.5tCK-tDQSS 1tCK +/- 1ns tCK/2 +/- 1ns tCK/2 +/- 1ns -Z +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -Y +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -0 +/- 0.8ns +/- 0.8ns +/- 0.6ns 0.6 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/-0.8ns +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 2.5tCK-tDQSS 1tCK +/- 0.75ns tCK/2 +/- 0.75ns tCK/2 +/- 0.75ns tRPST*1 tHZQ *1 *1 : Changed description method for the same functionality. This means no difference from the previous version. 3.Changed the following AC parameter symbol From. To. Output data access time from CK/CK tDQCK tAC Version 0.61(August 9,1999) - Changed the some values of "write with auto precharge" table for different bank in page 31. Asserted command Old Read Read + AP*1 Legal Legal For Different Bank 3 New Illegal Illegal Old Legal Legal 4 New Illegal Illegal -2- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Revision History(continued) Version 0.7 (March, 2000) - Changed 128Mb spec from target to Preliminary version. - Changed partnames as follows. from KM44L32031BT-G(L)Z/Y/0 KM48L16031BT-G(L)Z/Y/0 KM416L8031BT-G(L)Z/Y/0 - Changed input cap. spec. from CK/CK DQ/DQS/DM CMD/Addr 2.5pF ~ 3.5pF 4.0pF ~ 5.5pF 2.5pF ~ 3.5pF to 2.0pF ~ 3.0pF w/ Delta Cin = 0.25pF 4.0pF ~ 5.0pF w/ Delta Cin = 0.5pF 2.0pF ~ 3.0pF with Delta Cin = 0.5pF to K4H280438B-TC(L)A2/B0/A0 K4H280838B-TC(L)A2/B0/A0 K4H281638B-TC(L)A2/B0/A0 - Changed operating condition. from Vil/Vih(ac) VIL/VIH(dc) Vref +/- 0.35V Vref +/- 0.18V to Vref +/- 0.31V Vref +/- 0.15V - Added Overshoot/Undershoot spec . Vih(max) = 4.2V, the overshoot voltage duration is 3ns at VDD. . Vil(min) =- 1.5V, the overshoot voltage duration is 3ns at VSS. - Changed AC parameters as follows. from tDQSQ tDV tQH tHP - Added DC spec values. +/- 0.5(PC266), +/- 0.6(PC200) +/- 0.35tCK to +0.5(PC266), +0.6(PC200) tHPmin - 0.75ns(PC266) tHPmin - 1.0ns(PC200) tCLmin or tCHmin New Definition Removed New Definition Comments Version 0.71 (April, 2000) - Corrected a typo for tRAS at 133Mhz/CL2.5 from 48ns t0 45ns. - Corrected a typo in "General Information" table from 64Mx4 to 8Mx16. Version 0.72(May,2000) - Changed DC spec item & test condition Version 0.73(June,2000) - Added updated DC spec values - Deleted tDAL in AC parameter Version 1.0(November,2000) - Eliminate "preliminary" -3- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Contents Revision History General Information 1. Key Features 1.1 Features 1.2 Operating Frequencies 2. Package Pinout & Dimension 2.1 Package Pintout 2.2 Input/Output Function Description 2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension 3. Functional Description 3.1 Simplified State Diagram 3.2 Basic Functionality 3.2.1 Power-Up Sequence 3.2.2 Mode Register Definition 3.2.2.1 Mode Register Set(MRS) 3.2.2.2 Extended Mode Register Set(EMRS) 2 9 10 10 10 11 11 12 13 14 14 15 15 16 16 18 19 19 20 20 20 21 21 22 23 23 24 25 3.2.3 Precharge 3.2.4 No Operation(NOP) & Device Deselect 3.2.5 Row Active 3.2.6 Read Bank 3.2.7 Write Bank 3.3 Essential Functionality for DDR SDRAM 3.3.1 Burst Read Operation 3.3.2 Burst Write Operation 3.3.3 Read Interrupted by a Read 3.3.4 Read Interrupted by a Write & Burst Stop 3.3.5 Read Interrupted by a Precharge 3.3.6 Write Interrupted by a Write -4- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.7 Write Interrupted by a Read & DM 3.3.8 Write Interrupted by a Precharge & DM 3.3.9 Burst Stop 3.3.10 DM masking 3.3.11 Read With Auto Precharge 3.3.12 Write With Auto Precharge 3.3.13 Auto Refresh & Self Refresh 3.3.14 Power Down 26 27 28 29 30 31 32 33 34 4. Command Truth Table 5. Functional Truth Table 6. Absolute Maximum Rating 7. DC Operating Conditions & Specifications 7.1 DC Operating Conditions 7.2 DC Specifications 8. AC Operating Conditions & Timming Specification 8.1 AC Operating Conditions 8.2 AC Timming Parameters & Specification 9. AC Operating Test Conditions 10. Input/Output Capacitance 11. IBIS: I/V Characteristics for Input and Output Buffers 11.1 Normal strength driver 11.2 Half strength driver( will be included in the future) 12. QFC function QFC definition QFC timming on Read Operation QFC timming on Write operation with tDQSSmax QFC timming on Write operation with tDQSSmin QFC timming example for interrupted writes operation 35 40 40 41 42 42 43 45 45 46 46 48 Timing Diagram 49 49 49 50 50 51 52 -5- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM List of tables Table 1 : Operating frequency and DLL jitter Table 2. : Column address configurtion Table 3 : Input/Output function description Table 4 : Burst address ordering for burst length Table 5 : Bank selection for precharge by bank address bits Table 6 : Operating description when new command asserted while read with auto precharge is issued Table 7 : Operating description when new command asserted while write with auto precharge is issued Table 8 : Command truth table Table 9-1 : Functional truth table Table 9-2 : Functional truth table (contiued) Table 9-3 : Functional truth table (contiued) Table 9-4 : Functional truth table (contiued) Table 9-5 : Functional truth table (cotinued) Table 10 : Absolute maximum raings Table 11 : DC operating condtion Table 12 : DC specification Table 13 : AC operating condition Table 14 : AC timing parameters and specifications Table 15 : AC operating test conditions Table 16 : Input/Output capacitance Table 17 : Pull down and pull up current values 10 11 12 17 19 30 31 34 35 36 37 38 39 40 40 42 42 44 45 45 47 -6- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM List of figures Figure 1 : 128Mb Package Pinout Figure 2 : Package dimension Figure 3 :State digram Figure 4 : Power up and initialization sequence Figure 5 : Mode register set Figure 6 : Mode register set sequence Figure 7 : Extend mode register set Figure 8 : Bank activation command cycle timing Figure 9 : Burst read operation timing Figure 10 : Burst write operation timing Figure 11 : Read interrupted by a read timing Figure 12 : Read interrupted by a write and burst stop timing Figure 13 : Read interrupted by a precharge timing Figure 14 : Write interrupted by a write timing Figure 15 : Write interrupted by a read and DM timing Figure 16 : Write interrupted by a precharge and DM timing Figure 17 : Burst stop timing Figure 18 : DM masking timing Figure 19 : Read with auto precharge timing Figure 20 : Write with auto precharge timing Figure 21 : Auto refresh timing Figure 22 : Self refresh timing Figure 23 : Power down entry and exit timing Figure 24 : Output Load Circuit (SSTL_2) Figure 25 : I / V characteristics for input/output buffers: pull-up(above) and pull-down(below) Figure 26 : QFC timing on read operation Figure 27 : QFC timing on write operation with tDQSSmax Figure 28 : QFC timing on write operation with tDQSSmin Figure 29 : QFC timing example for interrupted writes operation 11 13 14 15 16 17 18 20 21 22 23 23 24 25 26 27 28 29 30 31 32 32 33 45 46 49 50 50 51 -7- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM General Information Organization 32Mx4 133Mhz w/ CL=2 K4H280438B-TCA2 K4H280438B-TLA2 16Mx8 K4H280838B-TCA2 K4H280838B-TLA2 8Mx16 K4H281638B-TCA2 K4H281638B-TLA2 133Mhz w/ CL=2.5 K4H280438B-TCB0 K4H280438B-TLB0 K4H280838B-TCB0 K4H280838B-TLB0 K4H281638B-TCB0 K4H281638B-TLB0 100Mhz w/ CL=2 K4H280438B-TCA0 K4H280438B-TLA0 K4H280838B-TCA0 K4H280838B-TLA0 K4H281638B-TCA0 K4H281638B-TLA0 1 2 3 4 5 6 7 8 9 10 11 K 4 H XX XX X X X - X X XX Memory DRAM Temperature & Power Small Classification Density and Refresh Organization Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification H : DDR SDRAM 4. Density & Refresh 64 : 64M 4K/64ms 28 : 128M 4K/64ms 56 : 256M 8K/64ms 51 : 512M 8K/64ms 1G : 1G 16K/32ms 5. Organization 04 : x4 08 : x8 16 : x16 32 : x32 6. Bank 3 : 4 Bank 7. Interface (VDD & VDDQ) 8: SSTL-2(2.5V, 2.5V) 8. Version M A B C D E : 1st Generation : 2nd Generation : 3rd Generation : 4th Generation : 5th Generation : 6th Generation Package Version Interface (VDD & VDDQ) Speed 9. Package T : TSOP2 (400mil x 875mil) 10. Temperature & Power C : (Commercial, Normal) L : (Commercial, Low) 11. Speed A0 : 10ns@CL2 A2 : 7.5ns@CL2 B0 : 7.5ns@CL2.5 -8- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 1. Key Features 1.1 Features * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Four banks operation * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock(CK) * Data I/O transactions on both edges of data strobe * Edge aligned data output, center aligned data input * LDM,UDM/DM for write masking only * Auto & Self refresh * 15.6us refresh interval(4K/64ms refresh) * Maximum burst refresh cycle : 8 * 66pin TSOP II package 1.2 Operating Frequencies - A2(DDR266A) Speed @CL2 Speed @CL2.5 DLL jitter 133MHz@CL2 0.75ns - B0(DDR266B) 100MHz 133MHz 0.75ns - A0(DDR200) 100MHz 0.8ns *CL : Cas Latency Table 1. Operating frequency and DLL jitter -9- REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 1. Package Pinout & Dimension 2.1 Package Pinout 8Mb x 16 16Mb x 8 32Mb x 4 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD QFC/NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH) Bank Address BA0-BA1 Row Address A0-A11 Auto Precharge A10 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 QFC/NC QFC/NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD MS-024FC 42 41 40 39 38 37 36 35 34 FIgure 1. 128Mb package Pinout Organization 32Mx4 16Mx8 8Mx16 Column Address A0-A9, A11 A0-A9 A0-A8 DM is internally loaded to match DQ and DQS identically. Table 2. Column address configuration - 10 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 2.2 Input/Output Function Description SYMBOL CK, CK TYPE Input DESCRIPTION Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. FET Control : Optional. Output during every Read and Write access. Can be used to control isolation switches on modules. No Connect : No internal electrical connection is present. DQ Power Supply : +2.5V 0.2V. DQ Ground. Power Supply : +2.5V 0.2V (device specific). Ground. SSTL_2 reference voltage. CKE Input CS Input RAS, CAS, WE LDM,(U)DM Input Input BA0, BA1 A [n : 0] Input Input DQ LDQS,(U)DQS I/O I/O QFC NC VDDQ VSSQ VDD VSS VREF Output Supply Supply Supply Supply Input Table 3. Input/Output Function Description - 11 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension Units : Millimeters (0.80) (0.50) (10x) (10x) 0.125 +0.075 -0.035 (0.50) 0x~8x (R 0. 25 ) ) (R 0.2 5 #66 #34 10.160.10 (1.50) #1 (1.50) #33 0.6650.05 0.2100.05 (0.80) ) 0. 15 ) 0.05 MIN (0.71) 0.65TYP 0.650.08 0.300.08 (10x) 0.10 MAX [ 0.075 MAX ] (4x ) (R 0.1 5 (10x) 1.20MAX 22.220.10 0.25TYP NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY (R Figure 2. Package dimension - 12 - REV. 1.0 November. 2. 2000 0.45~0.75 1.000.10 11.760.20 (10.76) 128Mb DDR SDRAM 3. Functional Description 3.1 Simplified State Diagram SELF REFRESH REFS REFSX MODE REGISTER SET MRS IDLE REFA AUTO REFRESH CKEL CKEH POWER DOWN CKEL CKEH ROW ACTIVE WRITE WRITEA WRITEA WRITE READA READ READ ACT POWER DOWN BURST STOP READ WRITEA READA PRE WRITEA PRE PRE READA READA POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence WRITEA : Write with autoprecharge READA : Read with autoprecharge Figure 3. State diagram - 13 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.2 Basic Functionality 3.2.1 Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. *1 5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to all of the rest address pins, A1~A11 and BA1) *1 6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0) *2 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command with low to A8 to initialize device operation. *1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. Power up & Initialization Sequence 0 CK CK Command precharge ALL Banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP EMRS 2 Clock min. 2 Clock min. precharge ALL Banks tRP 1st Auto Refresh tRFC tRFC 2 Clock min. Mode Register Set MRS DLL Reset 2nd Auto Refresh Any Command Figure 4. Power up and initialization sequence - 14 - REV. 1.0 November. 2. 2000 min.200 Cycle 128Mb DDR SDRAM 3.2.2 Mode Register Definition 3.2.2.1 Mode Register Set(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst lengths, addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus RFU 0 RFU DLL TM CAS Latency BT Burst Length Mode Register A8 0 1 DLL Reset No Yes A7 0 1 mode Normal Test A3 0 1 Burst Type Sequential Interleave Burst Length CAS Latency A6 BA0 0 1 An ~ A0 (Existing)MRS Cycle Extended Funtions(EMRS) 0 0 0 0 1 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Latency Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve Figure 5. Mode Register Set - 15 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Burst Address Ordering for Burst Length Burst Length 2 Starting Address(A2, A1, A0) xx0 xx1 x00 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Table 4. Burst address ordering for burst length DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the normal drive strength and weak drive strength will be included in a future revision of this document. Mode Register Set 0 CK CK Command tCK Precharge All Banks *1 Mode Register Set Any Command 1 2 3 4 5 6 7 8 tRP*2 2 Clock min. *1 : MRS can be issued only at all bank precharge state. *2 : Minimum tRP is required to issue MRS command. Figure 6. Mode Register Set sequence - 16 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.2.2.2 Extended Mode Register Set(EMRS) The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver size. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus RFU 1 RFU : Must be set "0" QFC D.I.C DLL Extended Mode Register Output Driver Impedence Control 0 1 Normal Weak A0 0 1 DLL Enable Enable Disable BA0 0 1 An ~ A0 (Existing)MRS Cycle Extended Funtions(EMRS) QFC control 0 1 Disable(Default) Enable Figure 7. Extend Mode Register set - 17 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.2.3 Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Bank Selection for Precharge by Bank address bits A10/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks Table 5. Bank selection for precharge by Bank address bits 3.2.4 No Operation(NOP) & Device Deselect The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. For both Deselect and NOP the device should finish the current operation when this command is issued. - 18 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.2.5 Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min). Bank Activation Command Cycle (CAS Latency = 2) 0 CK CK Address Command Bank A Row Addr. Bank A Activate Bank A Col. Addr. Write A with Auto Precharge ROW Cycle Time(tRC) Bank B Row Addr. Bank B Activate Bank A Row. Addr. Bank A Activate 1 2 Tn Tn+1 Tn+2 RAS-CAS delay(tRCD) NOP RAS-RAS delay time(tRRD) NOP : Dont care Figure 8. Bank activation command cycle timing 3.2.6 Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. 3.2.7 Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. - 19 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3 Essential Functionality for DDR SDRAM The essential functionality that is required for the DDR SDRAM device is described in this chapter 3.3.1 Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is completed. < Burst Length=4, CAS Latency= 2, 2.5 > 0 CK CK Command READ A NOP NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 DQS CAS Latency=2 DQ s DQS CAS Latency=2.5 DQ s tRPRE tRPST Dout 0 Dout 1 Dout 2 Dout 3 Dout 0 Dout 1 Dout 2 Dout 3 Figure 9. Burst read operation timing - 20 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.2 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. < Burst Length=4 > 0 CK CK Command DQS DQ s NOP WRITEA NOP WRITEB NOP NOP NOP NOP NOP 1 *1 2 3 4 5 6 7 8 tDQSSmax tWPRES*1 *1 Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3 Figure 10. Burst write operation timing 1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. - 21 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.3 Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. < Burst Length=4, CAS Latency=2 > 0 CK CK Command DQS CAS Latency=2 DQ s Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3 1 2 3 4 5 6 7 8 READ A READ B NOP NOP NOP NOP NOP NOP NOP Figure 11. Read interrupted by a read timing 3.3.4 Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ's(Output drivers) in a high impedance state. To insure the DQ's are tristated one cycle before the beginning the write operation, Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=2.5 before the Write command. < Burst Length=4, CAS Latency=2 > 0 CK CK Command DQS CAS Latency=2 DQ s Dout 0 Dout 1 Din 0 Din 1 Din 2 Din 3 1 2 3 4 5 6 7 8 READ Burst Stop NOP WRITE NOP NOP NOP NOP NOP Figure 12. Read interrupted by a write and burst stop timing. The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. - 22 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.5 Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. < Burst Length=8, CAS Latency=2 > 0 CK CK 1tCK 1 2 3 4 5 6 7 8 Command DQS CAS Latency=2 DQ s READ Precharge NOP NOP NOP NOP NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by precharge Figure 13. Read interrupted by a precharge timing When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS Precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock edge). In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. - 23 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.6 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. < Burst Length=4 > CK CK Command DQS DQ s Din A0 Din A1 Din B0 Din B1 Din B2 Din B3 0 1 1tCK 2 3 4 5 6 7 8 NOP WRITE A WRITE b NOP NOP NOP NOP NOP NOP Figure 14. Write interrupted by a write timing - 24 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.7 Write Interrupted by a Read & DM A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. < Burst Length=8, CAS Latency=2 > 0 CK CK Command DQS CAS Latency=2 DQ s tDQSSmin NOP WRITE NOP NOP NOP READ NOP NOP NOP 1 2 3 4 5 6 7 8 tDQSSmax tWPRES*5 Din 0 Din 1 Din 2 Din 3 tCDLR Din 4 Din 5 Din 6 Din 7 Dout 0 Dout 1 Dout 2 Do tCDLR DQS CAS Latency=2 DQ s DM tWPRES*5 Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout 0 Dout 1 Dout 2 Do Figure 15. Write interrupted by a read and DM timing The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed 2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM. 5. Refer to "3.3.2 Burst write operation" - 25 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.8 Write Interrupted by a Precharge & DM A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. < Burst Length=8 > CK CK Command DQS tWPRES*5 tWR Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 0 1 2 3 4 5 6 7 8 NOP WRITE A NOP NOP NOP NOP Precharge WRITEB NOP tDQSSmax DQ s tDQSSmin DQS DQ s DM tWPRES*5 Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 Figure 16. Write interrupted by a precharge and DM timing Precharge timing for Write operations in DRAMs requires enough time to allow "write recovery" which is the time required by a DRAM core to properly store a full "0" or "1" level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation, i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. - 26 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. 5. Refer to "3.3.2 Burst write operation" 3.3.9 Burst Stop The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation. < Burst Length=4, CAS Latency= 2, 2.5 > 0 CK CK Command DQS CAS Latency=2 DQ s DQS CAS Latency=2.5 DQ s Dout 0 Dout 1 Dout 0 Dout 1 The burst ends after a delay equal to the CAS latency. READ A Burst Stop NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 Figure 17. Burst stop timing The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required: 1. The BST command may only be issued on the rising edge of the input clock, CK. 2. BST is only a valid command during Read bursts. 3. BST during a Write burst is undefined and shall not be used. 4. BST applies to all burst lengths. 5. BST is an undefined command during Read with autoprecharge and shall not be used. - 27 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 6. When terminating a burst Read command, the BST command must be issued LBST ("BST Latency") clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2, 2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are optional). 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). 3.3.10 DM masking The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be issued at the rising or falling edge of data strobe. < Burst Length=8 > CK CK Command DQS DQ s DM masked by DM=H Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din7 0 1 2 3 4 5 6 7 8 WRITE NOP NOP NOP NOP NOP NOP NOP NOP tDQSS Figure 18. DM masking timing - 28 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.11 Read With Auto Precharge If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied. < Burst Length=4, CAS Latency= 2, 2.5> 0 CK CK Command DQS CAS Latency=2 DQ s DQS CAS Latency=2.5 DQ s Begin Auto-Precharge Dout 0 Dout 1 Dout 2 Dout 3 Dout 0 Dout 1 Dout 2 Dout 3 BANK A ACTIVE NOP READ A Auto Precharge NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 tRAS(min.) tRP * Bank can be reactivated at the completion of precharge Figure 19. Read with auto precharge timing When the Read with Auto precharge command is issued, new command can be asserted at 3,4 and 5 respectively as follows, Asserted command READ READ+AP Active Precharge *1 For same Bank 3 READ + No AP*1 READ + AP Illegal Legal 4 READ+ No AP READ + AP Illegal Legal 5 Illegal Illegal Illegal Illegal 3 Legal Legal Legal Legal For Different Bank 4 Legal Legal Legal Legal 5 Legal Legal Legal Legal : AP = Auto Precharge Table 6. Operating description when new command asserted while read with auto precharge is issued - 29 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.12 Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). < Burst Length=4 > 0 CK CK Command DQS DQ s Din 0 Din 1 Din 2 Din 3 * Bank can be reactivated at completion of tRP BANK A ACTIVE NOP WRITE A Auto Precharge NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 tWR tRP Internal precharge start Figure 20. Write with auto precharge timing Burst length = 4 Asserted command WRITE WRITE+ AP READ READ+AP Active Precharge *1 *2 For same Bank 3 WRITE+ No AP*1 WRITE+ AP Illegal Illegal Illegal Illegal 4 WRITE+ No AP WRITE+ AP READ+NO AP+DM *2 READ + AP+DM Illegal Illegal 5 WRITE+ No AP WRITE+ AP READ+NO AP+DM READ + AP+DM Illegal Illegal 6 Illegal Illegal READ+ NO AP READ + AP Illegal Illegal 7 Illegal Illegal READ+ NO AP READ + AP Illegal Illegal 8 Illegal Illegal Illegal Illegal Illegal Illegal 3 Legal Legal Illegal Illegal Legal Legal For Different Bank 4 Legal Legal Illegal Illegal Legal Legal 5 Legal Legal Legal Legal Legal Legal 6 Legal Legal Legal Legal Legal Legal 7 Legal Legal Legal Legal Legal Legal : AP = Auto Precharge : DM : Refer to " 3.3.7 Write Interrupted by a Read & DM " in page 25. Table 7. Operating description when new command asserted while write with auto precharge is issued - 30 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.13 Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). Command CKE = High PRE Auto Refresh CK CK CMD tRP tRFC Figure 21. Auto refresh timing Self Refresh A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL. Command CKE Self Refresh Active CK CK Read tXSA*1 tXSR*2 Figure 22. Self refresh timing 1. Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after any bank active command. 2. Exit self refresh to read command - 31 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 3.3.14 Power down The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tck+tIS prior to row active command . During power down mode, refresh operations cannot be performed, therefore the device cannot be remained in power down mode longer than the refresh period(Data retension time) of the device. CK CK Command Precharge Precharge power down Entry Active Active power down Entry Active power down Exit Read Figure 23. Power down entry and exit timing - 32 - REV. 1.0 November. 2. 2000 CKE 128Mb DDR SDRAM 4. Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A11, A9 ~ A0 Note H H H X X H L H X X L L L L H L L L L L H X L H L L L H X H L L L H H X H H V V OP CODE OP CODE X 1, 2 1, 2 3 3 3 3 L H H X Row Address L H L H X V X L H X Column Address (A0~A9) Column Address (A0~A9) Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable 4 4 4 4, 6 7 H H H X X X L L L H L X H L H L H H L X V X X H X V X L H H X V X X H X V L L L X V X X H X V V 5 Active Power Down H L H L H L X X L H H H X X H X H X 8 9 9 X H L X H Table 8. Command truth table (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2.EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. - 33 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 5. Functional Truth Table Current State PRECHARGE STANDBY CS L L L L L L ACTIVE STANDBY L L L L L L L READ L L L L L L L RAS CAS H H L L L L H H H L L L L H H H L L L L H L H H L L H L L H H L L H L L H H L L WE L X H L H L L H L H L H L L H L H L H L X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA ILLEGAL*4 AUTO-Refresh*5 Mode Register Set*5 NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 Action WRITE/WRITEA ILLEGAL Active PRE/PREA Refresh Bank Active/ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL Op-Code, Mode-Add MRS Table 9-1. Functional truth table - 34 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State WRITE CS L L RAS CAS H H H L WE L H X Address Command Burst Stop READ/READA ILLEGAL Action BA, CA, A10 Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 L L L L L READ with AUTO PRECHARGE*6 (READA) L L L L L L L WRITE with AUTO RECHARGE*7 (WRITEA) L L L L L L L H L L L L H H H L L L L H H H L L L L L H H L L H L L H H L L H L L H H L L L H L H L L H L H L H L L H L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Terminate Burst, Latch CA, WRITE/WRITEA Begin new Write, Determine Auto-Precharge*3 Active PRE/PREA Refresh MRS Burst Stop READ/READA Bank Active/ILLEGAL*2 Terminate Burst With DM=High, Precharge ILLEGAL ILLEGAL ILLEGAL *6 WRITE/WRITEA ILLEGAL Active PRE/PREA Refresh MRS Burst Stop READ/READA *6 *6 ILLEGAL ILLEGAL ILLEGAL *7 WRITE/WRITEA *7 Active PRE/PREA Refresh *7 *7 ILLEGAL ILLEGAL Op-Code, Mode-Add MRS Table 9-2. Functional truth table - 35 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State PRECHARGING (DURING tRP) CS L L L L L L RAS CAS H H L L L L H H L L L L H H H L L L L H L H H L L H L H H L L H L L H H L L WE L X H L H L L X H L H L L H L H L H L X Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ WRITE Active PRE/PREA Refresh MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 Action BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add NOP*4(Idle after tRP) ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 WRITE ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L L L L L L WRITE RECOVERING (DURING tWR OR tCDLR) L L L L L L L Table 9-3. Functional truth table - 36 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State REFRESHING CS L L L L L L RAS CAS H H L L L L H H L L L L H L H H L L H L H H L L WE L X H L H L L X H L H L X Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Action BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add MODE REGISTER SETTING L L L L L L Table 9-4. Functional truth table - 37 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State SELFREFRESHING*8 CKE n-1 L L L L L L CKE n H H H H H L H L H L L L L L L X H CS H L L L L X X X X L H L L L L X X RAS X H H H L X X X X L X H H H L X X CAS X H H L X X X X X L X H H L X X X WE X H L X X X X X X H X H L X X X X Add X X X Action Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOPeration(Maintain Self-Refresh) Exit Power Down(Idle after tPDEX) NOPeration(Maintain Power Down) Refer to Function True Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State=Power Down Refer to Function Truth Table X X X X X X X X X X X X X X POWER DOWN ALL BANKS IDLE*9 L L H H H H H H H L ANY STATE other than listed above H Table 9-5. Functional truth table ABBREVIATIONS : H=High Level, L=Low level, X=Dont Care Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to "3.3.11 Read with Auto Precharge" in page 29 for detailed information. 7. Refer to "3.3.12 Write with Auto Precharge" in page 30 for detailed information. 8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9. Power-Down and Self-Refresh can be entered only from All Bank Idle state. ILLEGAL = Device operation and/or data integrity are not guaranteed. - 38 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 6. Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1.0 50 Unit V V V C W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability Table 10. Absolute maximum ratings 7. DC Operating Conditions & Specifications 7.1 DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input leakage current Output leakage current Output High Current (VOUT = 1.95V) Output Low Current (VOUT = 0.35V) Symbol VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) II IOZ IOH IOL Min 2.3 2.3 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 Max 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 2 5 Unit Note V V V V V V V uA uA mA mA 3 1 2 Notes 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed 2% of the DC value 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. Table 11. DC operating condition - 39 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 7.2 DDR SDRAM SPEC Items and Test Conditions Conditions Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition Percharge power-down standby current; All banks idle; power - down mode; CKE = IDD1 IDD2P - - IDD2F - - IDD2Q - - IDD3P - - IDD3N - - IDD4R - - IDD4W - - IDD5 IDD6 IDD7 - - - 40 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 7.3 DDR SDRAM IDD spec table 32Mx4 K4H280438B-TCA2 (DDR266A) typical IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7 85 125 21 40 30 25 35 140 125 185 2 1 250 worst 95 140 25 45 35 30 40 155 140 200 2 1 265 K4H280438B-TCB0 (DDR266B) typical 85 125 21 40 30 25 35 140 125 185 2 1 250 worst 95 140 25 45 35 30 40 155 140 200 2 1 265 K4H280438B-TCA0 (DDR200) typical 75 120 18 35 25 20 30 115 100 175 2 1 240 worst 85 130 22 40 30 25 35 130 115 190 2 1 255 mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Symbol Unit Notes 16Mx8 K4H280838BT-CA2 (DDR266A) typical IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7 90 140 21 40 30 25 40 150 135 195 2 1 260 worst 95 150 25 45 35 30 45 165 150 205 2 1 280 K4H280838B-TCB0 (DDR266B) typical 90 140 21 40 30 25 40 150 135 195 2 1 260 worst 95 150 25 45 35 30 45 165 150 205 2 1 280 K4H280838B-TCA0 (DDR200) typical 80 125 19 35 27 20 30 125 105 180 2 1 250 worst 85 135 23 40 32 25 35 140 120 190 2 1 275 mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Symbol Unit Notes - 41 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 8Mx16 Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7 K4H281638B-TCA2 (DDR266A) typical 90 140 21 40 30 25 45 210 150 195 2 1 300 worst 95 155 25 45 35 30 50 245 165 210 2 1 340 K4H281638B-TCB0 (DDR266B) typical 90 140 21 40 30 25 45 210 150 195 2 1 300 worst 95 155 25 45 35 30 50 245 165 210 2 1 340 K4H281638B-TCA0 (DDR200) typical 80 135 20 35 27 20 35 155 110 180 2 1 275 worst 85 150 24 40 32 25 40 175 125 190 2 1 300 mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Unit Notes Table 12. 128Mb DDR SDRAM IDD SPEC Table < Detailed test conditions for DDR SDRAM IDD1 & IDD7 > IDD1 : Operating current: One bank operation 1. Typical Case : Vdd = 2.5V, T=25'C 2. Worst Case : Vdd = 2.7V, T= 10'C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP - 42 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM IDD7 : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25'C 2. Worst Case : Vdd = 2.7V, T= 10'C 3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP 8. AC Operating Conditions & Timming Specification 8.1 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.62 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 1 2 3 4 Note 1. Vih(max) = 4.2V. The overshoot voltage duration is 3ns at VDD. 2. Vil(min) = -1.5V. The undershoot voltage duration is 3ns at VSS. 3. VID is the magnitude of the difference between the input level on CK and the input on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Table 13. AC operating conditions - 43 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 8.2 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble Data out high impedence time from CK/CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command CL=2.0 CL=2.5 tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tHZQ tDQSS tWPRES tWPREH tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX tXSW 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.4 0.4 0.9 0.9 0.9 15 0.5 0.5 1.75 10 95 0.6 0.6 1.1 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK K4H281638B -TCA2 (DDR266A) Min 65 75 45 20 20 15 2 1 1 7.5 15 15 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 120K Max K4H281638B -TCB0 (DDR266B) Min 65 75 45 20 20 15 2 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.4 0.4 0.9 0.9 0.9 15 0.5 0.5 1.75 10 0.6 0.6 1.1 15 15 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 0.45 0.45 -0.8 -0.8 0.9 0.4 -0.8 0.75 0 0.25 0.4 0.4 0.9 1.1 1.1 16 0.6 0.6 2 10 116 0.6 0.6 1.1 120K Max K4H281638B -TCA0 (DDR200) Min 70 80 48 20 20 15 2 1 1 10 15 15 0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 +0.8 1.25 120K Max ns ns ns ns ns ns tCK tCK tCK ns ns tCK tCK ns ns ns tCK tCK ns tCK ns tCK tCK tCK tCK ns ns ns ns ns ns ns ns 3 2 Unit Note - 44 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Parameter Exit self refresh to bank active command Exit self refresh to read command Refresh interval time 64Mb, 128Mb 256Mb Output DQS valid window Clock half period DQS write postamble time QFC setup to first DQS edge on reads QFC hold after last DQS edge on reads Write command to QFC delay on write Write burst end to QFC delay on write Write burst end to QFC delay on write interrupted by Precharge Symbol tXSA tXSR tREF tQH tHP tWPST tQCS tQCH tQCSW tQCHW tQCHWI 1.25ns -A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2) Min 75 200 15.6 7.8 tHPmin -0.75ns tCLmin or tCHmin 0.25 0.9 0.4 Max Min 75 200 15.6 7.8 tHPmin -0.75ns tCLmin or tCHmin 0.25 Max Min 80 200 15.6 7.8 tHPmin -1.0ns tCLmin or tCHmin 0.25 Max ns Cycle us us ns ns tCK 4 1 1 7 Unit Note 1.1 0.6 4.0 0.5tCK 1.5tCK 0.9 0.4 1.1 0.6 4.0 0.9 0.4 1.1 0.6 4.0 tCK tCK ns 5 6 1.25ns - 0.5tCK 1.5tCK 1.25ns - 0.5tCK 1.5tCK 1. Maximum burst refresh of 8 2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. 3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC high. And the value of tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC high. 6. the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe edge to QFC high. 7. A write command can be applied with tRCD satisfied after this command. Table 14. AC timing parameters and specifications - 45 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 9. AC Operating Test Conditions (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70C) Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.5 * VDDQ 1.5 1.0 VREF+0.31/VREF-0.31 VREF Vtt See Load Circuit Unit V V V/ns V V V Note Table 15. AC operating test conditions Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ Figure 24. Output Load Circuit (SSTL_2) 10. Input/Output Capacitance (VDD=2.5, VDDQ=2.5V, TA= 25C, f=1MHz) Parameter Input capacitance (A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM) Symbol CIN1 CIN2 COUT CIN3 Min 2 2 4.0 4.0 Max 3.0 3.0 5.0 5.0 Delta Cap(max) 0.5 0.25 0.5 Unit pF pF pF pF Table 16. Input/output capacitance - 46 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 11. IBIS: I/V Characteristics for Input and Output Buffers 11.1 Normal strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 160 Maximum 140 120 Typical High Iout(mA) 100 80 60 Typical Low Minimum 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 Vout(V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 0.0 0 -20 -40 0.5 1.0 1.5 2.0 2.5 Minumum Typical Low Iout(mA) -60 -80 -100 -120 -140 -160 -180 -200 -220 Typical High Maximum Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2 Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) - 47 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 pullup Current (mA) Maximum 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Typical Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Typical High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Minimum 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Typical Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -41.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Typical High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Minimum -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Maximum -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2 Table 17. Pull down and pull up current values Temperature (Tambient) Typical Minimum Maximum Vdd/Vddq 25C 70C 0C Typical Minimum Maximum 2.5V 2.3V 2.7V The above characteristics are specified under best, worst and normal process variation/conditions - 48 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 11.2 Half strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 90 80 70 60 Maximum Iout(mA) Typical High Typical Low Minimum 40 30 20 10 Iout(mA) 0 0.0 1.0 2.0 50 Vout(V) 3. Thenominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 0.0 0 0.5 1.0 1.5 2.0 2.5 -10 -20 Iout(mA) -30 -40 -50 -60 Minumum Typical Low Typical High -70 -80 -90 Maximum Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2 Figure 26. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) - 49 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 pullup Current (mA) Maximum 5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 Typical Low 3.4 6.9 10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8 Typical High 3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 Minimum 2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 Typical Low -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 Typical High -4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 Minimum -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 Maximum -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7 Table 18. Pull down and pull up current values Temperature (Tambient) Typical Minimum Maximum Vdd/Vddq 25C 70C 0C Typical Minimum Maximum 2.5V 2.3V 2.7V The above characteristics are specified under best, worst and normal process variation/conditions - 50 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 12. QFC function QFC definition when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is also driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe transition is received. Whenever the device is in standby, the signal is HI-Z. DQS is intended to enable an external data switch. QFC can be enabled or disabled through EMRS control. QFC timing on Read operation QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of DQS postamble CL = 2, BL = 2 0 CK CK Command DQS DQ' S QFC 1 2 3 4 5 6 7 8 Read Dout 0 Dout 1 Hi-Z tQCS tQCH Figure 26. QFC timing on read operation - 51 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM QFC timing on Write operation QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge. 0 CK CK Command Write 1 2 3 4 5 6 7 8 BL = 2 DQS@tDQSSmax DQ' @tDQSSmax S QFC Hi-Z tQCSW Dout 0 Dout 1 *2 tQCHW max. *1tQCHW min. Figure 27. : QFC timing on write operation with tDQSSmax BL = 2 CK CK Command 0 1 2 3 4 5 6 7 8 Write DQS@tDQSSmin DQ' @tDQSSmin S QFC Hi-Z tQCSW Dout 0 Dout 1 *1 *2 tQCHW min. tQCHW max. Figure 28. : QFC timing on write operation with tDQSSmin 1. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC tri-state. 2. The value of tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC tri-state. - 52 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM QFC timing example for interrupted Writes operation BL = 8 CK CK Command 0 1 2 3 4 5 6 7 8 Write Precharge DQS DQ' S QFC Hi-Z tQCSW Dout 0 Dout 1 Dout 2 Dout 3 tQCHWI max Figure 29. : QFC timing example for Interrupted writes operation - 53 - REV. 1.0 November. 2. 2000 |
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